? semiconductor components industries, llc, 2005 november, 2005 ? rev. 2 1 publication order number: NUP4201MR6/d NUP4201MR6 low capacitance tsop?6 diode?tvs array for high speed data lines protection the NUP4201MR6 transient voltage suppressor is designed to protect high speed data lines from esd, eft, and lighting. features: ? low capacitance (3 pf maximum between i/o lines) ? esd rating of class 3b (exceeding 8 kv) per human body model and class c (exceeding 400 v) per machine model ? protection for the following iec standards: iec 61000?4?2 (esd) 15 kv (air) 8 kv (contact) iec 61000?4?4 (eft) 40 a (5/50 ns) iec 61000?4?5 (lighting) 23 a (8/20 s) ? ul flammability rating of 94 v?0 ? pb?free package is available typical applications: ? high speed communication line protection ? usb 1.1 and 2.0 power and data line protection ? digital video interface (dvi) ? monitors and flat panel displays maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak power dissipation 8 x 20 s @ t a = 25 c (note 1) p pk 500 w operating junction temperature range t j ?40 to +125 c storage temperature range t stg ?55 to +150 c lead solder temperature ? maximum (10 seconds) NUP4201MR6t1 NUP4201MR6t1g t l 235 260 c c human body model (hbm) machine model (mm) iec 61000?4?2 air (esd) iec 61000?4?2 contact (esd) esd 16000 400 20000 20000 v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. non?repetitive current pulse per figure 1 (pin 5 to pin 2) tsop?6 low capacitance diode tvs array 500 watts peak power 6 volts marking diagram device package shipping ordering information NUP4201MR6t1 tsop?6 3000/tape & ree l tsop?6 case 318g plastic 1 6 pin configuration and schematic 6 i/o 5 v p 4 i/o i/o 1 v n 2 i/o 3 http://onsemi.com 63 = specific device code m = date code = pb?free package (note: microdot may be in either location) 63 NUP4201MR6t1g tsop?6 (pb?free) 3000/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. m *date code orientation may vary depending upon manufacturing location.
NUP4201MR6 http://onsemi.com 2 electrical characteristics (t j =25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm (note 2) 5.0 v breakdown voltage v br i t =1 ma, (note 3) 6.0 v reverse leakage current i r v rwm = 5 v 5.0 a clamping voltage v c i pp = 5 a (note 4) 12.5 v clamping voltage v c i pp = 8 a (note 4) 20 v maximum peak pulse current i pp 8x20 s waveform 25 a junction capacitance c j v r = 0 v, f=1 mhz between i/o pins and gnd 3.0 5.0 pf junction capacitance c j v r = 0 v, f=1 mhz between i/o pins 1.5 3.0 pf 2. tvs devices are normally selected according to the working peak reverse voltage (v rwm ), which should be equal or greater than the dc or continuous peak operating voltage level. 3. v br is measured at pulse test current i t . 4. non?repetitive current pulse per figure 1 (pin 5 to pin 2) typical performance curves (t j = 25 c unless otherwise noted) figure 1. pulse derating curve 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 200 t a , ambient temperature ( c) figure 2. 8 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 0204060 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s 80 figure 3. junction capacitance vs reverse voltage 5.0 2.5 0.0 01 v br , reverse voltage (v) junction capacitance (pf) 2345 i/o lines i/o?ground peak power dissipation (%) 4.5 2.0 4.0 1.5 3.5 1.0 3.0 0.5 figure 4. clamping voltage vs. peak pulse current (8 x 20 s waveform) 20 10 0 010 peak pulse current (a) clamping voltage (v) 20 30 40 50 18 8 16 6 14 4 12 2
NUP4201MR6 http://onsemi.com 3 package dimensions tsop?6 case 318g?02 issue p 0.95 0.037 1.9 0.075 0.95 0.037 mm inches scale 10:1 1.0 0.039 2.4 0.094 0.7 0.028 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 23 4 5 6 d 1 e b e a1 a 0.05 (0.002) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. c l h e dim a min nom max min millimeters 0.90 1.00 1.10 0.035 inches a1 0.01 0.06 0.10 0.001 b 0.25 0.38 0.50 0.010 c 0.10 0.18 0.26 0.004 d 2.90 3.00 3.10 0.114 e 1.30 1.50 1.70 0.051 e 0.85 0.95 1.05 0.034 l 0.20 0.40 0.60 0.008 0.039 0.043 0.002 0.004 0.014 0.020 0.007 0.010 0.118 0.122 0.059 0.067 0.037 0.041 0.016 0.024 nom max 2.50 2.75 3.00 0.099 0.108 0.118 h e ? ? 0 1 0 0 1 0
NUP4201MR6 http://onsemi.com 4 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NUP4201MR6/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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